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CY62128E MoBL(R)
1-Mbit (128K x 8) Static RAM
Features
* Very high speed: 45 ns * Temperature ranges -- Industrial: -40C to +85C -- Automotive-A: -40C to +85C -- Automotive-E: -40C to +125C * Voltage range: 4.5V-5.5V * Pin compatible with CY62128B * Ultra low standby power -- Typical standby current: 1 A -- Maximum standby current: 4 A (Industrial) * Ultra low active power * * * * -- Typical active current: 1.3 mA @ f = 1 MHz Easy memory expansion with CE1, CE2 and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and 32-pin TSOP I packages
Functional Description[1]
The CY62128E is a high performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW) To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins.
Logic Block Diagram
CE1 CE2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WE OE
INPUT BUFFER
IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6
ROW DECODER
128K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO7
A12 A13
A14
A15
Note 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05485 Rev. *E
*
198 Champion Court
A16
*
San Jose, CA 95134-1709 * 408-943-2600 Revised May 07, 2007
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CY62128E MoBL(R)
Pin Configuration[2]
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3
32-Pin SOIC Top View
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 IO7 IO6 IO5 IO4 IO3
TSOP I Top View (not to scale)
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View (not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3
Product Portfolio
Power Dissipation Product Range VCC Range (V) Min CY62128ELL CY62128ELL Ind'l/Auto-A Auto-E 4.5 4.5 Typ[3] 5.0 5.0 Max 5.5 5.5 45
[4]
Speed (ns) Typ[3] 1.3 1.3
Operating ICC (mA) f = 1MHz Max 2 4 f = fmax Typ[3] 11 11 Max 16 35
Standby ISB2 (A) Typ[3] 1 1 Max 4 30
55
Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.
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CY62128E MoBL(R)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ...............................-0.5V to 6.0V (VCC(max) + 0.5V) DC Voltage Applied to Outputs in High-Z State[5, 6] ...............-0.5V to 6.0V (VCC(max) + 0.5V) DC Input Voltage[5, 6] ...........-0.5V to 6.0V (VCC(max) + 0.5V) Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA
Operating Range
Device Range Auto-E Ambient Temperature -40C to +125C VCC[7]
CY62128ELL Ind'l/Auto-A
-40C to +85C 4.5V to 5.5V
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB2 [8] Description Output HIGH Voltage Output LOW Voltage Test Conditions IOH = -1 mA IOL = 2.1 mA 2.2 -0.5 -1 -1 11 1.3 1 45 ns (Ind'l/Auto-A) Min 2.4 0.4 VCC + 0.5 0.8 +1 +1 16 2 4 2.2 -0.5 -4 -4 11 1.3 1 Typ[3] Max Min 2.4 0.4 VCC + 0.5 0.8 +4 +4 35 4 30 A 55 ns (Auto-E) Typ[3] Max Unit V V V V A A mA
Input HIGH Voltage VCC = 4.5V to 5.5V Input LOW voltage VCC = 4.5V to 5.5V Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power down Current--CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max)
Capacitance (For all Packages) [9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 9. Tested initially and after any design or process changes that may affect these parameters.
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CY62128E MoBL(R)
Thermal Resistance[9]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board SOIC Package 48.67 25.86 STSOP Package 32.56 3.59 TSOP Package 33.01 3.42 Unit C/W C/W
AC Test Loads and Waveforms
VCC OUTPUT R1 3.0V 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT Parameters R1 R2 RTH VTH Value 1800 990 639 1.77
RTH
V Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR [8] tCDR
[9]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC= VDR, CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Ind'l/Auto-A Auto-E
Min 2
Typ[3]
Max 4 30
Unit V A A ns ns
0 tRC
tR [10]
Data Retention Waveform[11]
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 2.0V
VCC(min)
tR
CE
Notes 10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
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CY62128E MoBL(R)
Switching Characteristics (Over the Operating Range)[12]
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[15] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[13, 14] Low-Z[13] 10 45 35 35 0 0 35 25 0 18 10 55 40 40 0 0 40 25 0 20 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to Low-Z[13] High-Z[13, 14]
[13]
Description
45 ns (Ind'l/Auto-A) Min 45 45 10 45 22 5 18 10 18 0 45 Max
55 ns (Auto-E) Min 55 55 10 55 25 5 20 10 20 0 55 Max
Unit
ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW and CE2 HIGH to Low-Z CE1 HIGH or CE2 LOW to
High-Z[13, 14]
CE1 LOW and CE2 HIGH to Power Up CE1 HIGH or CE2 LOW to Power Down
Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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CY62128E MoBL(R)
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [16, 17]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 17, 18]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Write Cycle No. 1 (WE Controlled) [11, 15, 19, 20]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA IO NOTE 21 tHZOE DATA VALID tHD
Notes: 16. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 19. Data IO is high impedance if OE = VIH. 20. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 21. During this period, the IOs are in output state and input signals must not be applied.
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CY62128E MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 19, 20]
tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tHA
CE
Write Cycle No. 3 (WE Controlled, OE LOW) [11, 20]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA IO NOTE 21 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Inputs/Outputs High-Z High-Z Data Out Data In High-Z Mode Deselect/Power down Deselect/Power down Read Write Selected, Outputs Disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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CY62128E MoBL(R)
Ordering Information
Speed (ns) 45 Ordering Code CY62128ELL-45SXI CY62128ELL-45ZAXI CY62128ELL-45ZXI 45 55 CY62128ELL-45SXA CY62128ELL-45ZXA CY62128ELL-55SXE CY62128ELL-55ZAXE Package Diagram Package Type Operating Range Industrial
51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85094 32-pin STSOP (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85094 32-pin TSOP Type I (Pb-free) 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85094 32-pin STSOP (Pb-free)
Automotive-A Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
16 1
0.546[13.868] 0.566[14.376]
0.440[11.176] 0.450[11.430]
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304]
0.101[2.565] 0.111[2.819]
0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE
51-85081-*B
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CY62128E MoBL(R)
Package Diagrams (continued)
Figure 2. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
51-85094-*D
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CY62128E MoBL(R)
Package Diagrams (continued)
Figure 3. 32-pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056
51-85056-*D
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62128E MoBL(R)
Document History Page
Document Title: CY62128E MoBL(R) 1-Mbit (128K x 8) Static RAM Document Number: 38-05485 REV. ** *A Orig. of ECN NO. Issue Date Change 203120 299472 See ECN See ECN AJU SYT New data sheet Converted from Advance Information to Preliminary Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively Changed tDOE from 15 ns to 18 ns for 35 ns speed bin Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns speed bins, respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins, respectively Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins, respectively Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins, respectively Added Pb-free package information Added footnote #9 Changed operating range for SOIC package from Commercial to Industrial Modified signal transition time from 5 ns to 3 ns in footnote #11 Changed max of ISB1, ISB2 and ICCDR from 1.0 A to 1.5 A Converted from Preliminary to Final Included Automotive Range and 55 ns speed bin Removed 35 ns speed bin Removed "L" version of CY62128E Removed Reverse TSOP I package from Product offering Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Removed ISB1 DC Specs from Electrical characteristics table Changed ISB2 (max) from 1.5 A to 4 A Changed ISB2 (Typ) from 0.5 A to 1 A Changed ICCDR (max) from 1.5 A to 4 A Changed the AC Test load Capacitance value from 100 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information Table Updated the Block Diagram on page # 1 Added footnote 4 on page 2 Added Automotive-A information Converted Automotive-E specs to final Added footnote #9 related to ISB2 and ICCDR Updated Ordering Information table Description of Change
*B
461631
See ECN
NXR
*C *D *E
464721 563144 1024520
See ECN See ECN See ECN
NXR AJU VKN
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